1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, more particularly to a semiconductor device and a manufacturing method thereof wherein a contact hole is formed on a doping region before forming a metal gate structure.
2. Description of the Prior Art
Poly-silicon is conventionally used as a gate electrode in semiconductor devices, such as metal-oxide-semiconductors (MOS). With the trend towards scaling down the size of semiconductor devices, conventional poly-silicon gates face problems such as boron penetration and unavoidable depletion effect leading to inferior performances. Because of these problems, the equivalent thickness of the gate dielectric layer increases, reducing the gate capacitance, and lowering a driving force of the devices. Therefore, work function metals that are suitable for use as high dielectric constant (high-k) gate dielectric layers are employed to replace the conventional poly-silicon gates as control electrodes.
In a complementary metal-oxide semiconductor (CMOS) device, one of the dual work function metal gate structures is used in an NMOS device and the other one is used in a PMOS device. It is well known that compatibility and process controls for the dual metal gate structure is more complicated, while thickness and composition controls for materials used in dual metal gate structure methods are more precise. The conventional dual metal gate structure methods are categorized into gate first processes and gate last processes. In a conventional dual metal gate structure method with the gate first process, both the annealing process for forming the source/drain ultra-shallow junction and the silicide process are performed after forming the metal gate structure. After performing the annealing process with a strict thermal budget, it is found that a flat band voltage (Vfb) does not increase nor decrease linearly with a decreasing EOT of the high-k gate dielectric layer; but a roll-off issue is observed. The gate last process is developed to improve the Vfb roll-off issue and avoid generating leakage current due to re-crystallization of the high-k gate dielectric layer occurring in high-temperature processes, to widen material choices for the high-k gate dielectric layer and to widen the choice for metal gate structure in the gate first process.
In the conventional gate last process, a sacrificial gate or a replacement gate is provided, and known processes are performed to build a normal MOS transistor. Then, the sacrificial/replacement gate is removed to form a gate trench. Metals are filled into the gate trench according to the electrical needs. For example, a work function metal layer, a barrier layer and a main electrode layer are formed in the gate trench. The process described above is generally regarded as a replacement metal gate (RMG) process. In the conventional process, an etching process is performed to form a contact plug on a doping region after the RMG process. An inter-layer dielectric with a substantial thickness over the doping region has to be penetrated by the contact plug, and it becomes more difficult to control the etching process.